Layout Verification​/PEX Engineer

Job Summary

The Psi Quantum Foundry Engineering team develops and supports a silicon photonics technology platform in collaboration with our development partners. This work includes enabling new materials, process modules, and technology capabilities required to support Psi Quantum's product development roadmap for a commercially useful quantum computer. The Layout Verification / Parasitic Extraction Engineer will support the physical and electrical verification of photonic integrated circuits within Psi Quantum's silicon photonics technology platform, focusing on validating the electrical routing associated with photonic circuits, including routing for photonic devices, bias lines, heaters, phase shifters, modulators, monitor structures, control signals, and electrical I/O interfaces.

• Run established DRC, LVS, ERC, antenna, density, and parasitic extraction flows using existing scripts, runsets, and foundry PDK decks.
• Validate electrical routing in photonic integrated circuit layouts, including routing for photonic devices, bias lines, heaters, phase shifters, modulators, monitor structures, control signals, and electrical I/O interfaces.
• Generate extracted netlists and extracted views for post-layout electrical simulation.
• Maintain organized logs, reports, run directories, and status trackers.
• Support block-level and chip-level verification activities prior to tapeout.

Required qualifications:

• Bachelor's degree in Electrical Engineering, Physics, Microelectronics, or related field, or equivalent experience.
• Basic knowledge of IC layout and physical verification concepts.
• Exposure to DRC, LVS, or parasitic extraction.
• Familiarity with Linux or Unix environments.
• Strong attention to detail and ability to follow established procedures.
• Good communication and documentation skills.
• Demonstrated interest in quantum computing.
• Ability to contribute in a fast-moving start-up environment.

Preferred qualifications:

• Exposure to analog/mixed-signal ICs, or custom IC layout.
• Experience with Cadence Virtuoso, Siemens Calibre, Cadence Pegasus/PVS, Cadence Quantus, and similar EDA tools.
• Familiarity with post-layout simulation flows and extracted netlists.
• Basic scripting experience in Python.
• Exposure to silicon photonics, photonic integrated circuits, or optoelectronics.
• Demonstrated interest in quantum computing, silicon photonics, or advanced semiconductor technology.

• U.S. Base Pay Range: $110,000–$150,000 USD
• Bay Area Pay Range: $150,000–$170,000 USD

Psi Quantum provides equal employment opportunity for all applicants and employees. Psi Quantum does not unlawfully discriminate on the basis of race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, gender expression, national origin, ancestry, citizenship, age, physical or mental disability, military or veteran status, marital status, domestic partner status, sexual orientation, genetic information, or any other basis protected by applicable laws.

Psi Quantum will only reach out to you using an official Psi Quantum email address and will never ask you for bank account information as part of the interview process. Please report any suspicious activity to