Principal Engineer, -Speed IO & Memory Systems

Principal Engineer, High-Speed IO & Memory Systems

Austin, Texas, United States;
San Jose, California, United States

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.

Samba Nova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the Samba Nova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

Samba Nova's Data Scale® platform pushes the limits of AI compute—and the integrity of every high-speed interface and memory subsystem is critical to its performance in the field. As a Principal Engineer, Post-Silicon Validation, you will own the bring-up, debug, and validation of high-speed IO and memory subsystems from first silicon through customer deployment.

This is a deeply technical, high-ownership role for an engineer who thrives on hard debug problems. You will operate across silicon, board, and software layers—leading cross-functional teams to root cause, driving issues to resolution, and building the infrastructure that makes future bring-up cycles faster and more reliable. If you have a bias for action, a sharp analytical mind, and the kind of depth that comes from years in post-silicon validation, this role was built for you.

System Bring-Up & Validation

• Own post-silicon bring-up and validation of high-speed IO and memory subsystems, including characterization, functional validation, stress testing, and performance analysis.
• Drive system power-on readiness—including debug infrastructure, tooling setup, and contingency planning—to enable first-pass bring-up success.

Debug & Cross-Functional Execution

• Lead system-level debug across silicon, board, and software layers, driving complex issues to verified root cause and resolution.
• Partner with design, firmware, verification, and systems teams to ensure timely bring-up and issue closure—without losing momentum.

Productization & Deployment

• Support product validation, deployment, and RMA debug in partnership with systems and customer engineering teams.
• Ensure product release readiness with a clear focus on stability, performance, and long-term field reliability.

Pre-Silicon & Design Feedback

• Review SoC architecture, board design, and SI/PI analysis through the lens of post-silicon debug and real-world deployment.
• Contribute to pre-silicon verification and emulation to improve bring-up efficiency and test coverage before first silicon arrives.

Infrastructure & Methodology

• Develop scripts and tooling to automate validation, debug, and data analysis workflows—reducing manual effort and accelerating iteration.
• Drive continuous improvement in post-silicon validation methodologies, debug infrastructure, and test scalability across product generations.

Required

• M.S. in Electrical Engineering or Computer Science.
• 7+ years of experience in post-silicon validation, system bring-up, or a closely related hardware engineering discipline.
• Hands-on experience with high-speed IO or memory protocols: PCIe, Ethernet, HBM, CXL, UCIe, or similar.
• Strong analytical skills applied to test development and data-driven debug.
• Scripting proficiency in Python, Bash, or equivalent.
• Demonstrated ability to lead cross-functional debugging efforts across hardware, firmware, and software teams.
• High ownership, self-starter mindset—you drive issues to closure without waiting to be asked.
• Clear and effective communicator with a proactive, collaborative approach to problem-solving.

Preferred

• Deep expertise in high-speed Ser Des training, adaptation, and equalization.
• Experience with mixed-signal IO design and validation.
• Hands-on…