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Senior RTL Verification Engineer - UVM & SystemVerilog
Job in
Palo Alto, Santa Clara County, California, 94306, USA
Listed on 2026-07-13
Listing for:
Entrada Ventures
Full Time
position Listed on 2026-07-13
Job specializations:
-
Engineering
Test Engineer
Job Description & How to Apply Below
Entrada Ventures is seeking a Senior RTL Verification Engineer to ensure the functionality and quality of complex digital designs across ASIC and FPGA platforms. You will build robust verification environments and drive coverage‑driven verification from planning through closure.
The ideal candidate has deep hands‑on System Verilog, UVM, and Python experience, plus familiarity with industry EDA tools and high‑speed interfaces such as PCIe and Ethernet, with a collaborative, detail‑oriented
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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