Principal Power Design Engineer

We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.

The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.

Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and empowered to do meaningful work alongside others who take the craft seriously.

We are seeking a Principal Power Design Engineer to own the design, implementation, and validation of the power delivery systems that support our high‑performance AI compute hardware.

AI compute systems create extreme, high‑frequency transient current steps that can destabilize hardware, introduce power supply noise, and corrupt sensitive high‑speed data links. In this role, you will be responsible for component selection, schematic design, layout oversight, and hands‑on lab validation of high‑current power subsystems. You will design and test multi‑phase voltage regulators, point‑of‑load converters, and sequencing circuitry to ensure our systems remain stable under demanding, dynamic AI inference workloads.

• Own hardware schematic design for multi‑phase buck regulators, point‑of‑load converters, and power sequencing circuitry.
• Select critical power components, including passives, inductors, power stages, controllers, and supporting circuitry.
• Define placement and routing constraints for board‑level power delivery networks, including decoupling capacitor strategy and high‑current power paths.
• Work closely with package engineering to ensure clean power delivery handoff at the socket or package interface.
• Lead lab validation of power subsystems, including VRM efficiency, loop stability, DC IR drop, thermal behavior, and transient response.
• Use oscilloscopes, electronic loads, network analyzers, thermal cameras, and related lab equipment to characterize power rails under maximum dynamic load conditions.
• Partner with SI/PI engineers to measure and mitigate power supply noise and Power Supply Induced Jitter on sensitive high‑speed lanes.
• Debug power integrity issues across board, package, silicon, firmware, workload, and system‑level interactions.
• Contribute to design guidelines, validation plans, and best practices for power delivery across the company’s hardware platforms.

• Extensive experience designing high‑current, multi‑phase DC‑DC regulators for high‑power ASICs, GPUs, processors, accelerators, or similar compute platforms.
• Strong background in power hardware design for systems with 500W+ devices or comparable high‑current power delivery requirements.
• Deep understanding of board‑level PDN implementation, decoupling strategy, power sequencing, transient response, and voltage regulation.
• Hands‑on experience with schematic capture and layout oversight for complex power delivery systems, preferably using tools such as Cadence Allegro or Concept.
• Strong lab validation skills using electronic loads, oscilloscopes, network analyzers for loop stability testing, thermal cameras, and related power measurement equipment.
• Experience characterizing VRM efficiency, bode plots, DC IR drop, ripple, noise, and transient behavior under dynamic workloads.
• Proficiency with SPICE‑based time‑domain circuit simulation or similar power simulation workflows.
• Ability to collaborate closely with SI/PI, package, hardware, firmware, and systems teams in a fast‑moving engineering environment.

• Experience with power delivery for AI accelerators, GPUs, networking ASICs, switch ASICs, or high‑performance server platforms.
• Familiarity with power integrity interactions affecting high‑speed Ser Des, PCIe, Ethernet, CXL, or other sensitive interfaces.
• Experience validating power systems under real workload conditions, including dynamic AI inference or high‑utilization compute workloads.