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Senior DFT Verification Engineer ASICs
Job in
Palo Alto, Santa Clara County, California, 94306, USA
Listed on 2026-07-14
Listing for:
Entrada Ventures
Full Time
position Listed on 2026-07-14
Job specializations:
-
Engineering
Test Engineer
Job Description & How to Apply Below
Entrada Ventures is seeking a Senior DFT Verification Engineer to drive robust verification for ASIC DFT logic across planning, development, and closure. You will build scalable environments, guide test strategies, and collaborate with DFT design and manufacturing teams to deliver high-quality silicon.
The role emphasizes hands-on System Verilog, UVM, and modern verification workflows, plus experience with scan/ATPG, JTAG, MBIST, and tester formats.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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