FPGA Design Engineer — RTL-to-Prototyping & Lab Validation
Job in
Palo Alto, Santa Clara County, California, 94306, USA
Listed on 2026-07-16
Listing for:
Drive Capital
Full Time
position Listed on 2026-07-16
Job specializations:
-
Engineering
Hardware Engineer, Test Engineer, Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Normal Computing is seeking an FPGA Design Engineer to bridge RTL and physical silicon. You will bring physics‑inspired ASIC designs to life on FPGA platforms for pre‑silicon validation and early software development, while building test infrastructure for post‑silicon bring‑up and characterization.
You will own RTL implementation, platform selection, IP integration, high‑speed I/O design, and a hardware‑software stack. Collaboration with silicon, EDA, and research teams is essential.
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