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Digital ASIC Verification Engineer; SystemVerilog​/UVM

Job in Palo Alto, Santa Clara County, California, 94306, USA
Listing for: SpaceX
Full Time position
Listed on 2026-07-27
Job specializations:
  • Engineering
    Test Engineer
Salary/Wage Range or Industry Benchmark: 135000 - 210000 USD Yearly USD 135000.00 210000.00 YEAR
Job Description & How to Apply Below
Position: Digital ASIC Verification Engineer (SystemVerilog/UVM)

SpaceX designs and tests next-generation ASICs for SpaceX satellites and ground systems. The role focuses on digital ASIC verification at block and system levels, with responsibilities spanning test plan creation, testbench development, and regression execution to ensure robust post-silicon validation.

Ideal candidates have a strong background in System Verilog, UVM, and Python for automation, plus experience with RTL and constrained random verification in a dynamic aerospace environment.

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