Senior RTL Design Engineer for Space-Grade SoC
Job in
Palo Alto, Santa Clara County, California, 94306, USA
Listed on 2026-08-12
Listing for:
SpaceX
Full Time
position Listed on 2026-08-12
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer, Hardware Engineer, Systems Engineer
Job Description & How to Apply Below
SpaceX is seeking a Senior RTL Design Engineer (Silicon Engineering) in California to develop next‑gen ASICs for Starlink and space networks. You will define architecture, write RTL in Verilog/System Verilog, and work with verification and physical teams to deliver timing‑clean designs.
Bachelor’s degree in EE/CE/CS and 5+ years RTL experience are required, with strengths in clock domain crossings, power optimization, and SoC integration; the role offers competitive compensation and stock options.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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