Advanced Packaging Engineer — Fiber Array Integration

Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.

Cspeed IO is developing next‑generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber‑optic technologies that overcome the limitations of existing optics solutions and architectures.

This position owns the detachable optical interface for CspeedIO optical engines: the on-package element, the coupling optics, the alignment features, and the high‑volume assembly process that joins fiber to engine without per-unit active alignment. A permanently bonded fiber array constrains the downstream flow in three respects: the engine cannot be optically qualified before fiber attach, a single failed channel scraps an assembly containing multiple high‑value die, and manual fiber handling limits automation.

A detachable interface addresses all three, enabling known‑good‑engine qualification, rework of failed units, and independent build and test of the fiber subassembly. Scope runs from interface architecture and tolerance budgeting through qualification and transfer of the production process to our assembly partners.

• Define the location of the detachability point and the partition between the permanently attached on-package element and the mateable plug.
• Define the coupling optics for the detachable path, including expanded-beam or collimated design, lens prescription and tolerancing, and the surface- versus edge-coupling trade‑off.
• Establish the alignment strategy — lithographically defined PIC features, precision mechanical datums, guide‑pin or V‑groove references — and the passive alignment capability it delivers.

• Own the insertion loss budget, including mated‑interface penalty, per‑channel uniformity across the array, and return loss.
• Develop the tolerance stack from PIC feature placement through package assembly to plug geometry using statistical methods, with a per‑port loss distribution as the deliverable.
• Specify and demonstrate repeatability across mate and demate cycles, and interchangeability across plug units and suppliers.
• Quantify positional and angular sensitivity and define the budget the mechanical design must hold.

• Eliminate per‑unit active alignment from the engine assembly flow. Where it cannot be eliminated, relocate it to a separately built and tested subassembly.
• Qualify reflow survivability of the on‑package element and compatibility with the assembly flows our OSATs operate.
• Define automated mating requirements: insertion force, blind‑mate behavior, retention, and hands‑off assembly tooling.
• Establish Cpk on passive placement and coupling loss, with associated SPC limits, yield reporting, and failure taxonomy.
• Maintain the per‑port cost and cycle‑time model covering alignment, mating and cleaning time, rework, and connector BOM.

• Define the contamination control strategy: dust caps, handling protocol, cleaning process and tooling, inspection criteria, and particle‑size sensitivity for the selected beam geometry.
• Define serviceability requirements: authorized personnel, permitted mating cycles, required training and tooling, and diagnostic criteria distinguishing contamination from mechanical damage.
• Define the rework and RMA flow for the optical interface.

• Qualify the mated interface.
• Characterize insertion loss drift across mating cycles and environmental exposure.
• Conduct root‑cause analysis of degradation across coupling optics, alignment features, latch mechanics, and contamination.

• Monitor and, where appropriate, participate in relevant standards and consortium activity…