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AI-Driven RTL Architect -Chip Interconnect
Job in
Palo Alto, Santa Clara County, California, 94306, USA
Listed on 2026-09-07
Listing for:
Kindredventures
Full Time
position Listed on 2026-09-07
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer
Job Description & How to Apply Below
Architect, a frontier AI lab for chip design, seeks a Founding Member of the Technical Staff to own the AI‑driven RTL design of interconnect fabrics and NoC routers for production silicon.
You will define block-level microarchitectures, specify interfaces, and lead collaboration with DV, SW, and ML teams to optimize latency, bandwidth, and power while enabling FPGA prototyping for early validation.
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