Senior SoC Compute​/Memory Subsystem Architect

Senior SoC Compute/Memory Subsystem Architect

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.

We are seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.

This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.

Key responsibilities will include but not limited to:

• Compute Subsystem Architecture
• Cache Hierarchy and Coherency Architecture
• Memory Subsystem Architecture
• IO Memory and Virtualization Architecture (SMMU/IOMMU)
• System-Level Integration (Compute Network Storage)
• Power, Efficiency, and Scaling Strategy
• Multi-Generation Architecture Roadmap
• Cross-Functional Leadership

Behavioral traits that we are looking for: (soft skills that you would like to see in a candidate)

• Strategic thinker:
  Ability to define long-term architecture vision and align stakeholders
• Technical leadership:
  Influences across teams without direct authority
• Problem solver:
  Approaches complex system challenges with structured thinking
• Collaboration:
  
  Builds strong partnerships across engineering disciplines
• Customer-focused mindset:
  Translates real-world workload needs into solutions
• Adaptability:
  Navigates ambiguity and evolving technical requirements
• Ownership mindset:
  Drives initiatives from concept through execution

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.

See Intel Benefits for more details.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Note:

For information on Intel's immigration sponsorship guidelines, please see

Intel U.S. Immigration Sponsorship Information

Minimum Qualifications and

Experience:

• Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.
• You must have 7 + years of experience in the following:
• SoC / CPU / memory subsystem architecture CPU architecture and cache hierarchies
• Memory subsystems (DDR/HBM, controllers, QoS)
  Coherent/Non-Coherent interconnect architectures
• Experience in system-level performance and PPA tradeoff analysis
• Drive architecture definition from concept to silicon

Preferred Qualifications and

Experience:

• Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
• ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures.
• Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments
• Familiarity with PCIe, CXL, and memory semantics for high performance IO.
• Track record of multi generation architectural ownership and mentoring other architects.

Experienced Hire

Shift 1 (United States of America)

US, California, Santa Clara

US, Arizona, Phoenix, US, California, Folsom, US, California, San Jose, US, Colorado, Fort Collins, US, Texas, Austin

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and…