Senior Pre-Silicon Verification Engineer

#
** Welcome!**## .We are seeking a Senior Mixed Signal Verification Engineer specializing in clock generator IP verification to ensure functional correctness of PLL/FLL designs. This role combines digital verification expertise with mixed-signal validation capabilities, requiring collaboration across architecture, RTL development, and analog design teams to deliver high-quality clock generation solutions.
** Key Responsibilities**- Perform comprehensive functional verification of clock generator IPs including PLL/FLL to ensure designs meet specification requirements
** Specialized Knowledge** - Knowledge of clock generation architectures and timing analysis
- Familiarity with analog verification methodologies and tools

- Experience with clock domain crossing verification and analysis
** Core Competencies** - Strong analytical and problem-solving skills for complex verification challenges
- Ability to work independently while collaborating effectively across multiple teams
- Excellent documentation and communication skills for technical reviews

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
** Minimum Qualifications
** 3+ yearsof experience in Design Verification and Validation methodologies with UVM, System Verilog, and industry-standard EDA tools 3+ yearsof experience in scripting languages such as Python and Perl
** Preferred Qualifications
** Experience with debug methodologies

- Experience with RTL development and design implementation
- Experience working on PLL/FLL or SoC clocking architectures and verification
** What We Offer*
* #J-18808-Ljbffr