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Principal -Speed Analog Layout Engineer

Job in Phoenix, Maricopa County, Arizona, 85003, USA
Listing for: Chelsea Search Group
Full Time position
Listed on 2026-02-15
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Position: Principal High-Speed Analog Layout Engineer

Principal High-Speed Analog Layout Engineer

US Citizen or US Permanent Resident preferred

Full-time Employee + Bonus, Benefits, 401k, Stock Options

Responsibilities
  • Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
  • Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
  • Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
  • Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
  • Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
  • Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
  • Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
Required
  • Minimum 5+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
  • Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
  • At least 1 year of experience with TSMC FinFET process nodes (3nm N3, 5nm N5, 7nm N7, or 16nm N16)
  • Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
  • Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
  • Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
  • Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
  • Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
  • Experience working in collaborative environments with international and remote teams
  • Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
  • Experience using revision control systems for layout design management
Preferred
  • Exposure to optical or high-speed analog interfaces is a strong plus
  • Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
  • Proven ability to collaborate with international teams
  • Strong organizational skills with high attention to detail and follow-through
  • Ability to multi-task and prioritize in a fast-paced, dynamic environment
  • Proactive, eager-to-learn mindset with excellent problem-solving skills

IC MASK LAYOUT DESIGN GROUP on Linked In: IC MASK LAYOUT DESIGN GROUP on Linked In

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