Packaging Customer Engineer

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** Welcome!**## .Packaging Customer Engineer page is loaded## Packaging Customer Engineer locations:
US, Arizona, Phoenix:
US, California, Santa Claratime type:
Full time posted on:
Posted Todayjob requisition :
JR0280776#
** Job Details:**##

Job Description:

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

The IFS Packaging and Test Business Group Packaging is a critical revenue enabler for IFS and a key part of Intel's forward-looking strategy. IFS Packaging Test Business Group has been created to develop, grow, and execute a robust packaging roadmap.

The primary responsibilities for the Packaging Customer Engineer will include but are not limited to:
Collaborate with IFS Customer product design, internal product design, Silicon process development, Intel's Assembly Test Technology Development (ATTD), and Product Engineering teams to drive product architecture definition, product package design and execution.

Serve as the engineering interface to IFS Customers for packaging services to promote Intel packaging technologies, to perform technical feasibility and risk assessments, to analyze product ask vs. the ATTD packaging roadmap and to close the deal with the customer.

Drive Customer-facing technology reviews as the key engineering interface between the Customer and Intel Foundry, owning the Customer packaging engineering relationship from product concept through product mass production.

Work with IFS Business Development, ATTD, ATM and Supply Chain to complete RFQ risk assessments and pricing assessments.

Capture customer feedback and competitive trends that can better inform the ATTD packaging roadmap.

Represent the customer in internal technology working groups for new technologies during pathfinding and development.

This position deals with a high level of both technology and market/business ambiguity and future uncertainties. In addition, this person will be frequently interacting and making recommendations to Intel VPs and Corporate VPs and will need to be conversant and knowledgeable in both internal roadmaps and external industry  this role you will need the following attributes:

Strong problem solving, analytical, and communication skills.

Have demonstrated the ability to plan and manage projects.

Extensive knowledge of Intel packaging development and manufacturing capabilities.

Experience in ATTD and Competitor packaging roadmaps.

Experience with product architecture floor plans, IP development cycles, and their dependency on package design and  able to work independently in a highly matrixed structure with extensive experience presenting to Senior Management (VP and Corporate VP Level).##
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* Qualifications:

** Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Job posting details (such as work model, location, or time type) are subject to change.

Minimum Qualifications
* Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field.
* ** 9+
** years of experience in semiconductor packaging
* Hands-on experience in one or more of the following areas:
+ Power delivery  + High‑speed signaling  + Thermal‑mechanical analysis  + Process development  + Die disaggregation architectures
* Experience presenting technical information to external customers and suppliers.
** Preferred Qualifications
*** Master’s or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM discipline.
Strong knowledge of Intel packaging technologies.
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