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Senior Clock-Gen IP Verification Engineer; PLL/FLL
Job in
Phoenix, Maricopa County, Arizona, 85003, USA
Listed on 2026-02-23
Listing for:
Intel Corporation
Full Time
position Listed on 2026-02-23
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Test Engineer
Job Description & How to Apply Below
A leading technology company in Phoenix is seeking a Senior Mixed Signal Verification Engineer specializing in clock generator IP verification. This role requires collaboration across architecture, RTL development, and analog design teams to ensure the functional correctness of PLL/FLL designs. Ideal candidates will have strong verification skills, experience with UVM and System Verilog, and proficiency in scripting languages like Python.
This position offers an opportunity to work on high-quality clock generation solutions.
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Position Requirements
10+ Years
work experience
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