Senior Physical Design Application Engineer

Job Details

Location:

Phoenix, Arizona (US) with additional locations in Santa Clara, California and Hillsboro, Oregon.

Job type:
Experienced Hire.

Shift: Shift 1 (United States of America).

Business group:
The Central Engineering Group (CEG) – focuses on customer‑driven, end‑to‑end solutions for advanced semiconductor design.

We seek a Senior Applications and Solutions Engineer to provide technical support to Intel Foundry Services customers on PDKs, digital reference flows, and design sign‑off methodologies with a specialized focus on Cadence tool suites. This role drives quality improvements in design kits via ASIC design reference flow validation and supports customers through successful tape‑outs.

• Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design sign‑off methodologies.
• Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to address customer issues and ensure successful tape‑outs.
• Drive customer success through expert guidance on advanced CMOS process implementation.
• Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review.
• Create application notes, technical content, and deliver training presentations to customers and internal teams.
• Establish and maintain quality assurance processes for design flow validation.
• Develop and optimize digital design implementation flows for advanced CMOS processes.
• Support hierarchical and multi‑voltage domain design approaches, timing, and physical convergence.
• Build and maintain quality assurance regression frameworks for design validation.

• Self‑driven and results‑oriented with ability to manage multiple tasks effectively.
• Strong teamwork skills to drive solutions for customer design implementation challenges.
• Analytical problem‑solving capabilities for complex design issues.
• Excellent communication skills with experience in collaboration and customer feedback.

• US citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a STEM‑related field.
• 4+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of experience in ASIC physical design implementation and/or ASIC design sign‑off (SoC/ASIC).
• 3+ years of experience in one of the following scripting languages:
  Python, Perl, Tcl, or shell scripting.

• Active US Government Security Clearance with a minimum of Secret level.
• Post‑graduate degree in Electrical or Computer Engineering, Computer Science, or a related STEM field.
• Customer‑facing experience in technical support roles.
• Experience with state‑of‑the‑art process technology (7nm and below).
• Hands‑on experience in Cadence EDA‑based ASIC design implementation, including full‑chip integration, synthesis, APR, static timing analysis, layout verification, and reliability verification.
• Proficiency with Cadence EDA tools and flows:
  Innovus, Tempus, Tempus
  
  ECO, Pegasus, Voltus.
• Experience with Synopsys tools (Fusion Compiler, Prime Time, Prime
  
  ECO, ICV) is a plus.
• Experience with hierarchical and multi‑voltage domain design, top‑down design, budgeting, and correlation across implementation and verification tools.

• Opportunity to work with cutting‑edge digital design technologies for foundry services.
• Direct customer engagement and technical leadership in advanced semiconductor design.
• Access to Intel’s most advanced foundry technologies and comprehensive EDA tool suites.
• Competitive compensation.
• Professional development in digital design methodologies and foundry services.
• Direct impact on foundry customer success and advanced semiconductor innovation.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that includes competitive pay, stock bonuses, and benefit programs, including health, retirement, and vacation. For more information about benefits of working at Intel or the work model for this role, please refer to internal resources.

Intel is committed to Responsible Business Alliance compliance and ethical hiring practices. No fees are required during the hiring process. If you are asked to pay any fees during the hiring process, please report this immediately.

Required skills:

Python, Shell Scripting, Perl.

Required language:
English.