CPU Formal Verification Engineer

Role Impact

As a Formal Verification Engineer, you will play a pivotal role in ensuring the quality and reliability of Intel’s cutting‑edge CPU technologies. Working as part of the CPU team, you will leverage formal verification methodologies to develop, implement, and validate the next generation of high-performance CPUs that power a variety of innovative devices, from laptops to AI and machine learning systems.

Your work directly impacts Intel’s ability to deliver world‑class products.

• Own the formal verification of microarchitecture blocks, methodologies, and critical aspects of CPU designs.
• Develop comprehensive formal verification strategies, plans, and proofs aligned with microarchitecture specifications.
• Create abstraction models to simplify design complexity and ensure convergence on validation.
• Collaborate with architects, RTL developers, and physical design teams to enhance verification efficiency.
• Analyze, debug, and resolve issues identified during verification, documenting findings and corrective actions.
• Develop and document formal verification test plans and conduct technical reviews with design and architecture teams.
• Maintain and innovate formal verification infrastructure and methodologies to streamline development.
• Mentor junior engineers and contribute to the growth of technical expertise within the team.
• Support post‑silicon failure debug and resolution efforts when required.

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field with 8+ years of relevant experience; or Master’s degree with 6+ years; or PhD with 4+ years.
• Experience in 3 or more of the following areas:

• Proficiency in formal verification, including industry‑standard tools such as Jasper Gold, Questa Formal, or VC Formal.
• Strong understanding of computer architecture fundamentals, microarchitecture, and memory systems.
• Hands‑on experience with hardware modeling languages, including System Verilog or Verilog.
• Proficiency in scripting or programming languages such as Python, Perl, C/C++, or TCL.
• Experience in assertion writing, coverage analysis, and failure debugging.

• Familiarity with x86 architecture, ISA, and system architecture.
• Experience with post‑silicon validation and debugging.
• Demonstrated technical innovation through research publications, patents, or advanced validation methods.
• Strong communication and collaboration skills, with a track record of teamwork in cross‑functional environments.

• Job Type: Experienced Hire
• Shift: Shift1 (United States of America)
• Primary
  
  Location:
  
  US, Oregon, Hillsboro
• Additional Locations: US, Arizona, Phoenix; US, California, Folsom; US, California, Santa Clara; US, Texas, Austin
• Business Group:
  Silicon and Platform Engineering Group (SPE)

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that includes competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation.

$ – $ USD (minimum and maximum target compensation for the position across all US locations). Individual pay is determined by location and other factors.

This role will be eligible for a hybrid work model, allowing employees to split time between on‑site and off‑site work.