Silicon Packaging Design Engineer

Job Details

Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving the end-to-end development of silicon interposer and bridge designs that define the future of computing and connectivity. As a key contributor to Intel's cutting‑edge technology, you will play a pivotal role in bridging silicon and hardware design, optimizing package performance, and delivering high‑impact solutions that meet performance, cost, and manufacturability goals.

Your expertise will directly contribute to Intel's mission to create world‑changing technology that improves lives and connects communities worldwide.

• Design and implement physical layout and routing of silicon interposers and embedded bridges.
• Perform substrate fit and routing studies to evaluate design tradeoffs in performance, cost, and manufacturability.
• Collaborate closely with silicon, technology development and hardware teams to optimize system-level design, including silicon-package-board integration and pinout.
• Propose design updates changes for rules and conduct internal and external reviews to ensure design feasibility.
• Analyze design data and resolve design rule checks (DRCs) to achieve optimized and manufacturable package designs.
• Utilize industry-leading electronic design automation (EDA) tools, including Virtuoso, Innovus, Fusion Compiler, ICvalidator, and Calibre, to create robust package layouts.
• Document processes and design specifications in the product lifecycle management system to ensure traceability and efficient collaboration.
• Conduct reviews with partner teams to close milestone requirements.

• Bachelor’s degree with 3+ years of experience or Master’s degree with 2+ years of experience in Electrical Engineering, Computer Engineering, or a STEM related field.

• Proficiency in custom layout and Auto‑place‑and‑route EDA tools including Virtuoso, Innovus, Fusion Compiler, ICvalidator, and/or Calibre.
• Experience with silicon physical layout design and development, routing interconnects, and/or review tools.

• At least 1 year of experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O fundamentals.
• At least 1 year of experience of Power Distribution and power integrity assessments.
• At least 1 year of experience of reliability requirements for interconnects.

• Familiarity with industry‑leading silicon physical design methodologies and workflows.
• Ability to effectively collaborate across multi‑disciplinary teams and communicate technical concepts clearly.
• A passion for innovation, problem‑solving, and continuous improvement in a fast‑paced environment.
• Prior experience in optimizing silicon performance and conducting trade‑off studies for advanced packaging designs.

Primary

Location:

US, Arizona, Phoenix. Additional Locations: US, Oregon, Hillsboro.

Experienced Hire.

Shift 1 (United States of America).

We offer a total compensation package that includes competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range: $ – $ USD. The range reflects the minimum and maximum target compensation for the position across all US locations; individual pay is determined by work location and additional factors.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

This role will require an on‑site presence.