Design Technology Tool Enablement Engineer

Job Overview

Join the Design Technology Platform team and contribute to Intel’s mission of delivering industry‑leading process technologies and cutting‑edge products to the market. As an EDA Tools Software Engineer you will design, develop, test, and debug software tools and flows that empower design teams to innovate faster and meet complex manufacturability requirements.

• Design, develop, and debug software tools and methodologies for process design and manufacturing.
• Collaborate with process developers, design rule owners, and end users to define technology specifications and requirements and implement optimal solutions.
• Automate workflows to enhance efficiency, accuracy, and deployment across teams.
• Build and execute test cases to validate software tools, ensuring seamless integration with design methodologies.
• Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specifications.
• Assess and isolate performance contributors for technology features as part of enablement.
• Identify and analyze problems, plans, tasks, and solutions.
• Cultivate and reinforce appropriate group values, norms, and behaviors.
• Perform in a dynamic, challenging, and sometimes ambiguous environment with drive and creativity.

• Creative, independent, and out‑of‑the‑box thinker with strong problem‑solving skills and analytical ability.
• Attention to detail, strong organization skills, and breadth to connect dots across disciplines.
• Self‑motivated with strong leadership skills and ability to influence across internal and external ecosystems.
• Excellent written and verbal communication skills for presenting complex issues with clarity.
• Soft skills to collaborate with cross‑functional and cross‑site teams and influence stakeholders.
• Ability to work in a dynamic and team environment.

• Master’s degree in Electrical Engineering, Computer Engineering, or related STEM field with 8+ years of experience, or Ph.D. with 5+ years of experience.
• At least 3 years of scripting experience (Python, Tcl, Perl) for automation or testing in Unix/Linux environments.
• At least 3 years of experience with EDA tools such as Calibre, ICV, or Pegasus, including rule deck development (e.g., SVRF/TVF, PXL, PVL).
• At least 5 years of experience in semiconductor device physics and/or process technology, design rules, and translating physical design challenges into algorithmic and software solutions.

• Familiarity with physical verification techniques (DRC, LVS, density/fill modules).
• Exposure to layout and schematic entry tools such as Cadence Virtuoso or Synopsys Custom Designer.
• Demonstrated ability to collaborate across teams and organizations to deliver innovative solutions.
• Strong analytical and problem‑solving skills addressing cross‑disciplinary challenges.
• Leadership experience driving process improvements or innovation initiatives.

Primary location: US, Oregon, Hillsboro. Additional locations: US, Arizona, Phoenix; US, California, Santa Clara.

This role qualifies for a hybrid work model, allowing employees to split their time between on‑site and off‑site work.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law.

Competitive pay, stock bonuses, and benefits programs including health, retirement, and vacation. Annual salary range for US positions: $–$ USD (range reflects target compensation; individual pay depends on location and experience).