Mixed Signal Logic Design Engineer

Job Details:

Job Description:

As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs r contributions will directly impact the development of cutting-edge technologies that enable the integration of functional units, IP blocks, and subsystems into full chip designs. This position is at the forefront of innovation, requiring collaboration with cross-functional teams to define architecture and microarchitecture features, optimize performance, and ensure design integrity.

Your work will drive Intel's success in achieving power, performance, and area goals, empowering our customers with industry-leading solutions.

Key Responsibilities:

* Develop architecture and microarchitecture specifications for the logic components and contribute to the overall system architecture decisions

* Implement specifications/designs in RTL and coordinate the work of other junior designers to deliver high-quality, complex logic blocks

* Develop behavioral models that represent analog and mixed-signal circuit blocks using System Verilog

* Run simulations and debug using logic, mixed-signal validation and AMS simulation tools

* Ensure high-quality designs by using industry standard tools such as linting and CDC analysis

* Support the physical design team in implementing your designs, including synthesis and timing closure

* Work with the pre-silicon validation/verification team to develop test plans and verification collateral

* Work with post-silicon validation teams to resolve post-silicon issues

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Knowledge and/or experience listed below would be obtained through a combination of your school, work and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

* BS degree in Electrical Engineering or Computer Engineering or similar field of study with 4+ years relevant experience

* -OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 3+ years relevant experience.

* Experience with standard digital design concepts such as FSM design techniques

* Experience with System Verilog

* Experience with computer architecture, analog design, ADC/DAC designs, communications theory, and/or microarchitecture design concepts

* Experience producing high-level architecture that meets internal and industry-standard specifications.

* Comfortable working with a high level of independence.

* Experience with multiple clock-domain design

Preferred Qualifications:

* BS degree in Electrical Engineering or Computer Engineering or similar field of study with 10+ years relevant experience

* -OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 8+ years relevant experience.

* Able to work highly independently, guide other junior team members and make contributions that increase the productivity of the entire design team

* Excellent communication and interpersonal skills

* Experience with both logic and analog circuits as well as with analog behavioral modeling

* Knowledge of mixed-signal validation, signal and systems analysis

* Knowledge of High-Speed I/O protocol stacks (UCIe, PCIe, USB, etc.)

* Experience with scripting languages e.g. Perl, bash/csh and Python is highly desirable

* Proven record of coordinating/guiding other designers to deliver large complex logic blocks

* Experience using RTL quality tools such as linting and CDC analysis and supporting team adoption and usage

* Experience with low-power design, power gating and multiple power-domain design

* Experience with writing, testing, packaging and releasing firmware

* Experience writing, testing and supporting front-end automation and packaging flows

* Experience using AI tools as a productivity booster in all aspects of the IP design process

* Strong analytical debugging skills, with a creative approach to problem-solving

Join us in redefining technology and engineering challenges. Apply today and become part of a team where your expertise drives meaningful change and innovation.

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary

Location:

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified…