Physical Design Engineer- Foundry Services

Overview

As a Physical Design Engineer, you will be responsible for transforming design concepts into manufacturable solutions, focusing on Si Interposers and Bridge designs. Your work will ensure high-performance, power efficiency, and area optimization, directly impacting Intel’s delivery of cutting‑edge technology to a global market. This role requires US citizenship.

• Perform physical design implementation of Si Interposer designs, progressing from floor planning to creating a database ready for manufacturing.
• Conduct all aspects of the physical design flow, including place and route, floor planning, routing, and physical design verification.
• Execute signal integrity analysis, power analysis, and reliability analysis to ensure design integrity.
• Perform verification and sign‑off, including formal equivalence verification, reliability verification, layout verification, electrical rule checking, and structural design checking.
• Analyze verification results, recommending and implementing fixes for violations.
• Optimize designs for product‑level parameters such as signal integrity, power, reliability, density, and area.
• Utilize industry‑standard EDA tools for physical design processes, including placing, routing, and analysis.
• Design and manage multiple power domains, static and dynamic power integrity, and report generation.
• Participate in the development and automation of physical design methodologies and flows to improve efficiency and scalability.
• Collaborate with cross‑functional teams to enable seamless integration of physical design across multiple projects.
• Drive enhancements in physical design methodologies and automation.
• Communicate and collaborate effectively within cross‑functional teams.
• Possess passion for solving complex design challenges and contributing to innovative solutions.

• US Citizenship.
• Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of experience, or a Master’s degree with 3+ years of experience.

• Experience with EDA tools for custom physical design and auto‑place‑and‑route (Virtuoso, Innovus, ICC/ICC2/Fusion, ic Validator, Calibre, UPF, RTL, SPICE, OASIS, ODB++).
• Experience with at least two of the following: floor planning, route optimization/shielding, signal integrity analysis, power delivery design/analysis for multi‑power domains, and reliability verification.
• Full chip physical design completion and verification for tape‑in/tape‑out.

• Experience optimizing designs for signal integrity and power integrity.
• Experience in chip‑level design and tape‑in assembly for advanced technology nodes.

Experienced Hire

Shift 1 (United States of America)

US, Arizona, Phoenix

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs performed in the US: $ -  USD.

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.