Senior Analog Design Engineer

Job Description

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry-defining analog and mixed-signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die‑to‑die interfaces across multiple advanced process nodes. We are seeking an experienced Senior Analog Design Engineer to join our engineering team. The successful candidate will design, develop, and optimize analog and mixed‑signal integrated circuits for various applications and lead complex projects from concept to production.

• Design and simulate analog and mixed-signal circuits including amplifiers, data converters, voltage regulators, PLLs, and other analog building blocks.
• Develop circuit architectures and perform detailed transistor‑level design.
• Create and optimize layouts working closely with layout engineers.
• Perform circuit analysis, simulation, and verification using industry-standard tools (Cadence, Synopsys, etc.) and leverage automation and AI-supported solutions.

• Lead analog design projects from specification to silicon validation.
• Mentor junior engineers and provide technical guidance.
• Collaborate with cross‑functional teams including architecture, logic, verification, physical design, layout, post‑silicon manufacturing, validation teams, and SOC partners.
• Drive design reviews and ensure adherence to design methodologies.
• Facilitate design development and convergence across global teams designing concurrently in numerous process nodes, working with teams in the US and India.

• Develop test plans and oversee silicon characterization.
• Debug and resolve design issues during pre‑ and post‑silicon phases.
• Optimize designs for performance, power, and area requirements.
• Ensure designs meet specifications and industry standards.

• Good communication and documentation skills, with a collaborative and proactive work style.
• Demonstrated ability to work effectively in cross‑functional, global teams and contribute to technical reviews.
• Strong analytical thinking, hands‑on debugging skills, and an eagerness to learn and share expertise within the team.

In this role, you will drive the definition, design, and verification of high-performance analog blocks, IP top-level designs, and subsystems (floor planning, power delivery, bump maps), collaborating closely with system architects, logic designers, and layout engineers. You will facilitate technical discussions, hold design reviews, and play an active role in post‑silicon validation and performance optimization. The position involves providing guidance to layout engineers and mentoring junior analog designers as needed.

Strong problem-solving skills, teamwork, and a willingness to share knowledge are essential. This role offers an opportunity to develop innovative designs and be part of a highly experienced IO and die‑to‑die design team focused on delivering next‑generation high-speed interconnect solutions. This is an on-site role and you are expected to work in the office at least 4 days per week.

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field.
• 6+ years of experience in analog/mixed-signal circuit design for high-speed Ser Des or similar applications.

• Proven experience in one or more of PLL, CDR, CTLE, DFE, ADC, RX AFE, Transmitter (TX), Power Delivery design, IP floor planning, IP top-level performance simulation, signal integrity analysis.
• High-speed IO calibration and training algorithms.
• High-speed communication standards such as UCIE and PCIe (Gen5/Gen6/Gen7).
• Core analog design principles, including noise, linearity, matching, and stability.
• Hands‑on experience with advanced FinFET CMOS process technologies.
• Analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.
• Post-silicon validation, lab measurements, and debugging of analog circuits.

• Master's degree in Electrical Engineering, Electronics Engineering, or a related…