Product Development Engineer - Scan Diagnostics

Overview

As a Product Development Engineer – Scan Diagnostics, you will play a core role in shaping Intel’s product innovation and manufacturing excellence. Your efforts will transform cutting‑edge integrated circuits from design feasibility to high‑volume production, providing broad exposure to the entire semiconductor product lifecycle. You will collaborate with cross‑functional teams to influence product design, ensure seamless production ramp‑up, and directly contribute to delivering world‑class solutions to Intel customers.

• Create, enable and support scan/chain diagnosis infrastructure and processes for Intel’s HVM products.
• Support fail‑based and volume diagnostic analysis and yield analysis requests to drive continuous yield improvement.
• Support CAD infrastructure and computational resources for diagnostics across all HVM product lines.
• Develop and optimize tools, methods, and flows for Design for Test (DFT), diagnostics, and yield analysis.
• Collaborate with external vendors and internal teams to establish standard industry practices for diagnostics and yield analysis.
• Maintain relationships with Electronic Design Automation (EDA) vendors to access the latest tools and methodologies.
• Facilitate knowledge transfer to ensure the Yield Management and Failure Analysis team members are updated with the latest methodologies and tools.
• Define and monitor DFX quality metrics (coverage, test cost, and debuggability) from development to production ramp‑up.
• Work closely with Design and New Product Introduction (NPI) teams to ensure diagnostic readiness for new products.

• Minimum qualifications:
  
  Bachelor’s degree in engineering or related field;
  Master’s degree or Ph.D. preferred; 4+ years of experience in DFT, scan diagnostics enablement, post‑Si diagnostics debug, yield analysis, and/or EDA tools.
• Proficiency in at least one scripting language such as Python, TCL, C‑Shell, or PERL.
• Strong communication and teamwork skills.
• Preferred:
  
  Experience with Siemens’ Tessent Test and Yield Analysis tools or similar;
  Synopsys’ Yield Explorer or similar; SOC/IP DFT control architecture (e.g., JTAG, IJTAG, IEEE
  1500); custom and/or ASIC circuit design.

• Competitive pay, stock bonuses, and benefit programs including health, retirement, and vacation.
• Hybrid work model allowing on‑site and off‑site work.
• Annual salary range (US): $141,910 – $269,100.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.