IP Design Verification Engineer

## IP Design Verification Engineer Apply locations:
US, Arizona, Phoenix:
US, Oregon, Hillsboro:
US, California, Folsom:
US, California, Santa Claratime type:
Full time posted on:
Posted Yesterday job requisition :
JR0284908#
** Job Details:**##

Job Description:

Join Intel as a Mixed Signal Design Verification Engineer and play a critical role in shaping the future of cutting-edge technology. In this position, you will ensure the functionality and performance of Intel's mixed signal components, which are essential to delivering world-class semiconductor solutions. By collaborating with cross-functional teams, you will drive the verification process to meet rigorous design, power, and performance specifications, ensuring Intel remains a leader in innovation.

Your contributions will directly impact product reliability, efficiency, and overall design excellence on a global scale.
** The primary responsibilities for this role will include, but are not limited to:
*** Develop and execute comprehensive mixed-signal IP verification plans to ensure designs meet specifications.
* Create and maintain test benches and verification environments using advanced methodologies such as UVM and OVM.
* Perform analog behavioral modeling to validate design functionality, timing, and power objectives.
* Identify, replicate, and debug presilicon bugs, root cause issues, and drive corrective measures.
* Analyze coverage metrics to ensure verification completeness and propose improvements where needed.
* Collaborate across disciplines to refine verification strategies, optimize designs, and achieve project goals.
* Document test plans, methodologies, and results, and lead technical reviews with cross-functional teams.
* Maintain and enhance existing verification infrastructure and methodologies to support evolving design challenges.##
*
* Qualifications:

**** Minimum Qualifications**:

Minimum qualifications are required to be initially considered for this position.
* Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 4 or more years of experience;
Master's degree with 3 or more years of experience; or PhD with no experience.* +3 years of experience in:  + System Verilog, Verilog, and advanced verification methodologies such as UVM and OVM.  + industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium/Jasper Gold, or Mentor Questa  + Analog behavioral modeling, high-speed IO IP verification, or low-power validation.  + Strong debugging skills in both analog and digital domains.  

+ PCIe and/or UCIe protocols.  + Test planning, test environment development, and test content development.
*
* Preferred Qualifications:

** Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
* Experience collaborating in cross-functional environments to solve complex problems.
* Proven ability to execute tasks with discipline and deliver results under tight timelines.
* Excellent written and verbal communication skills to document and present technical concepts effectively.

We invite you to bring your expertise and passion to Intel, where you can make a meaningful impact on the future of technology. Apply now and join a team that values your contributions and supports your growth.## Job Type:Experienced Hire##

Shift: Shift 1 (United States of America)## Primary

Location:

US, Arizona, Phoenix## Additional Locations:

US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro## Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.## Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## Benefits We offer a total compensation package that ranks among the best in the industry.

It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working ual Salary Range for jobs which could be performed in the US: $- USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work…