Senior CPU RTL Design Engineer – Power Management

What You’ll Do

• Define, design, and implement CPU microarchitecture features
• Develop and deliver RTL (System Verilog/Verilog) for CPU IP blocks
• Drive power, performance, and area (PPA) optimization, with a strong focus on
  • Power‑aware RTL design
  • Energy‑efficient architectures
• Design and validate multi‑clock domain and CDC solutions
• Contribute to CPU power management features, including
  • Dynamic voltage and frequency scaling (DVFS)
  • Power/thermal management
  • Reset flows and power state transitions (P/C states)
• Debug complex RTL and collaborate with verification teams
• Partner with SoC integration teams for full‑chip delivery
• Contribute to design methodology improvements and scalability

• Ownership & Accountability – operates independently with minimal guidance
• Depth over keywords – demonstrates hands‑on expertise (not just tool exposure)
• Problem‑solving rigor – able to debug and resolve complex design issues
• Collaboration mindset – works effectively across cross‑functional teams
• Technical leadership – influences design decisions and drives best practices
• Bias for action & urgency – maintains strong execution pace in fast‑moving environment

Bachelor’s degree in Electrical/Computer Engineering, Computer Science or related field with 9+ years of relevant experience. Or a Master's degree with 7+ years of experience.

• Experience with power management concepts (e.g., DVFS, power states, budgeting)
• Experience in low‑power / power‑aware CPU or SoC RTL design
• RTL development (Verilog/System Verilog)
• Debug and system‑level design understanding

• Experience in multi‑clock domain / CDC design
• Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.
• Experience with high‑speed circuit design and optimization, specifically for datapath, circuits, and arrays.
• Familiarity with circuit planning and timing convergence processes.
• Ability to leverage broad understanding of CPU architecture to deliver impactful solutions.
• Proficient with static timing analysis, UPF and lint checks.

Experienced Hire

Shift 1 (United States of America)

US, Texas, Austin

US, Arizona, Phoenix

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.

Compensation includes competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US: $ -  USD.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.