Memory Circuit Design Engineer

Job Details

Job Description:

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings.

We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace.

Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.

You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:

• Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
• Memory bit-cell and complex periphery IC layout and automation.
• Memory array/IP design, memory circuit innovation, test-chip design.
• Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.

Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.

• Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
• Design trade-offs between power, performance, and area (PPA).
• Custom digital circuit design, simulation, layout design, and verification.
• Knowledge of EDA tools used for custom digital and memory circuit design.

• PhD with 1-2 years of professional experience gained through either internships or full-time employment.
• Design technology co-optimization (DTCO).
• Post-Si validation experience.
• Knowledge of the CMOS ASIC design flow.

Experienced Hire

Shift 1 (United States of America)

US, Oregon, Hillsboro

US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

$ -  USD

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.