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Sr. CPU RTL Front End Methodology Engineer

Job in Phoenix, Maricopa County, Arizona, 85003, USA
Listing for: Intel
Full Time position
Listed on 2026-07-09
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 160000 USD Yearly USD 120000.00 160000.00 YEAR
Job Description & How to Apply Below

Position Summary

Senior CPU RTL Methodology Engineer – responsible for leading and executing RTL design, debug, and optimization for high‑performance Intel microprocessors, with a focus on AI‑enabled methodologies.

Responsibilities
  • Leverage AI tools and methodologies to drive efficiency gains in RTL coding and silicon development.
  • Advance front‑end methodologies and contribute to architectural and microarchitectural discussions to enhance scalability and flexibility.
  • Develop and implement strategies, tools, and techniques for RTL development and logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as physical design integrity.
  • Maintain comprehensive understanding of front‑end and back‑end flows, delivering solutions across multiple domains.
  • Collaborate effectively with architecture, backend, and other design teams to deliver industry‑leading products.
  • Build and sustain a high‑performing, technically strong organization by fostering and upholding core values, norms, and behaviors.
Behavioral Traits
  • Excellent problem‑solving and analytical skills.
  • Strong written and verbal communication.
  • Ability to work effectively in a fast‑paced, collaborative environment.
Minimum Qualifications
  • Bachelor’s degree in Computer Science, Electrical/Electronics/Engineering, or related field with 12+ years of work experience OR
  • Master’s degree in Computer Science, Electrical/Electronics/Engineering, or related field with 10+ years of work experience OR
  • PhD in Computer Science, Electrical/Electronics/Engineering, or related field with 6+ years of work experience.
  • 6+ years of experience in silicon development of CPU logic.
  • 5+ years of experience in technical leadership and delivering successful IP projects.
Preferred Qualifications
  • Experience on x86 CPU microarchitecture.
  • Experience with x86 memory management execution.
  • Experience driving front‑end methodologies and championing the use of AI tools to realize tangible product‑level benefits.
Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, national origin, disability, or any other characteristic protected by law.

Job Details

Job Type: Experienced Hire
Shift: Shift 1 (U.S.)
Location: Austin, Texas (primary) – optional sites in Phoenix, Arizona and Hillsboro, Oregon.
Work Model: On‑site presence required.

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