Analog Design Engineering Manager

Senior Analog Design Engineering Manager

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is responsible for delivering industry-defining analog and mixed-signal IP for Intel's Client, Datacenter, AI and Foundry customers. The IO team owns high-speed serial IO and die-to-die interfaces across multiple advanced process nodes. As a senior analog design engineering manager, you will lead technical teams to deliver IP that will shape Intel's future of IO and chiplet interconnect technology.

This engineering manager role will be responsible for the following:

• Technical Leadership:
  Guiding the design of analog circuits (e.g., ADCs/DACs, Phase Interpolators, voltage regulators) and ensure high-quality silicon through all phases of planning, tech readiness, pre-silicon design, and post-silicon validation.
• Project Management:
  Create detailed execution plans, manage schedules, resources, dependencies, and deliverables to meet IP milestones and SOC TI deadlines.
• Team Management and Development:
  Hire, develop, and mentor a team of analog design engineers with skillsets ranging from introductory to senior analog leads. Direct report team will be located in the US and will be about 10-15 engineers. This role is also expected to direct the work of, grow, and give feedback for team members from the broader org who are working on projects led by this manager.
• Cross-functional Collaboration:
  
  Partner with IP leads across domains (architecture, logic, physical design and layout), with key SOC design team members, and with post-silicon validation teams throughout the IP design and productization lifecycle.
• Culture and Work Environment:
  This leader must drive results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.

This is an on-site role and you are expected to work in the office at least 4 days per week.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field with 12+ years of experience
• 8+ years in a management or leadership role
• Proven expertise in analog IP development and delivering from concept to launch.
• Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.
• Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.
• Excellent communication, documentation, and presentation skills to audiences ranging from individual contributors to technical leaders and executives.

Preferred Qualifications:

• PhD or Master's degree in Electrical Engineering, Electronics Engineering, or related field.
• 12+ years in a management or leadership role
• 8+ years of experience managing analog IP design teams.
• Hands-on design experience in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, Transmitter (TX) design, or Receiver (RX) design.
• Deep knowledge of high speed serial IO technologies such as PCIe/CXL and USB Type C and of die to die technologies such as UCIe.
• 10+ years of proven success building, leading, and driving execution in silicon teams delivering to complex, high-impact programs.

Experienced Hire

Shift 1 (United States of America)

US, Arizona, Phoenix

US, Oregon, Hillsboro

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

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