Semiconductor Packaging Research Engineer

Job Details:

Job Description:

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Life at Intel

The Semiconductor Packaging Research Engineer drives technology research for advanced packaging and heterogeneous integration. The role is suited for candidates with expertise in either packaging process integration or modeling/simulation, with a focus on evaluating new architectures, materials, interconnects, reliability risks, and manufacturability trade-offs for future products.

• Research advanced packaging concepts such as chiplets, heterogeneous integration, 2.5D/3
  
  DIC, hybrid bonding, interposer, and die-to-die interconnects.
• Drive either process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and technology readiness.
• For process integration:
  • Define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation paths.
• For modeling:
  • Develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure analysis data.
• Translate product needs into research hypotheses, technical plans, and recommendations; document outputs through reports, design guidance, IP, publications, and development-transfer inputs.
• Collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams.
• For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Master’s or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or related field.
• 1+ years’ experience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration.
• 1+ years' experience in one or more of the following areas: process integration, research vehicle execution, DOE, defect/yield learning, reliability, model development& validation, or multi-physics simulation.
• 1+ years' experience with advanced packaging technologies such as flip chip, chiplets, 2.5D/3
  
  DIC, fan-out, hybrid bonding, interposers, HBM integration, advanced substrates, or die-to-die interconnects.

• Ph.D. or deep technical specialization in packaging process integration, computational mechanics, thermal sciences, electrical modeling, materials reliability, or microelectronics research and 4+ years of relevant experience.
• Experience with prototype builds, technology readiness assessment, research-to-development transfer, package-system co-optimization, or chip-package-board co-design.
• Modeling tool experience such as ANSYS, Abaqus, COMSOL, HFSS, Cadence, MATLAB, Python, JMP, or equivalent platforms.
• Record of patents, publications, conference presentations, technical reports, methodology development, or competitive technology assessments.
• Ability to turn ambiguous research problems into clear assumptions, experiments, learning milestones, qualification metrics, and actionable recommendations.

• Advanced packaging research and pathfinding
• Process integration or modeling/simulation expertise
• Heterogeneous integration, chiplet, and advanced substrate knowledge
• DOE, prototype learning, reliability assessment, or model validation
• Technology readiness evaluation and cross-functional communication

• Research outputs identify credible integration options, technology limiters, and trade-offs for future platforms.
• Process integration or modeling results are supported by clear assumptions, evidence, validation data, and documented limitations.
• Prototype, DOE, or simulation learning…