Senior Physical Design Application Engineer

About Intel Foundry

Intel Foundry is a systems foundry transforming the global semiconductor industry by delivering cutting‑edge silicon process and packaging technology leadership for the AI era. Intel Foundry will be differentiated from other foundries by our world‑class industry‑leading IP portfolio that customers can choose from including a rich IP ecosystem featuring x86 cores, graphics, AI, and Arm/RISC‑V IPs, world‑class design services, and operationally resilient global manufacturing with committed capacity in the US and Europe.

We seek a Senior Applications and Solutions Engineer to provide technical support to Intel Foundry Services customers on PDKs, digital reference flows, and design signoff methodologies with specialized focus on Cadence tool suites. This role drives quality improvements in design kits through ASIC design reference flow validation and supports customers through successful tape‑outs.

Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies; support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to address customer issues and ensure successful tape‑outs; drive customer success through expert guidance on advanced CMOS process implementation.

Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review; create application notes, technical content, and deliver training presentations to customers and internal teams; establish and maintain quality assurance processes for design flow validation.

Develop and optimize digital design implementation flows for advanced CMOS processes; support hierarchical and multi‑voltage domain design approaches, timing and physical convergence; build and maintain quality assurance (QA) regression frameworks for design validation.

• Self‑driven and results‑oriented with ability to manage multiple tasks effectively.
• Strong teamwork skills to drive solutions for customer design implementation challenges.
• Analytical problem‑solving capabilities for complex design issues.
• Excellent communication skills with experience in collaboration and customer feedback.

• US citizenship required; ability to obtain a US Government Security Clearance.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM‑related field of study.
• 4+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of experience in ASIC physical design implementation and/or ASIC design signoff (SoC/ASIC).
• 3+ years of experience in one of the following scripting languages (Python, Perl, Tcl, shell scripting).

• Active US Government Security Clearance with a minimum of Secret level.
• Post‑graduate degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field of study.
• Customer‑facing experience in technical support roles.
• Experience with state‑of‑the‑art process technology (7nm and below).
• Hands‑on experience in Cadence EDA‑based ASIC design implementation including full‑chip integration, synthesis, APR, static timing analysis, layout verification, and reliability verification.
• Proficiency with Cadence EDA tools and flows:
  Innovus, Tempus, Tempus
  
  ECO, Pegasus, Voltus.
• Experience with Synopsys tools (Fusion Compiler, Prime Time, Prime
  
  ECO, ICV) is a plus.
• Experience with hierarchical and multi‑voltage domain design, top‑down design, budgeting, and correlation across implementation and verification tools.

• Opportunity to work with cutting‑edge digital design technologies for foundry services.
• Direct customer engagement and technical leadership in advanced semiconductor design.
• Access to Intel’s most advanced foundry technologies and comprehensive EDA tool suites.
• Competitive compensation.
• Professional development in digital design methodologies and foundry services.
• Direct impact on foundry customer…