Principal Design Engineer

Principal Technical Leader

Team Credo is seeking a principal technical leader to drive both hands-on digital ASIC design and strategic architecture direction for our High-Performance Network Interface IP portfolio. This role has direct impact on the interconnect infrastructure enabling next-generation AI and HPC systems. Depending on the candidate's strengths, the focus may span from leading RTL development and design execution to shaping product roadmaps, architecture requirements, and long-range technology investments.

The ideal candidate brings deep expertise in computing and communication systems
-including memory subsystems, inter- and intra-chip interconnects, Ethernet, CXL, PCIe, UCIe, and UALink - and understands how these technologies support scalable AI infrastructure across accelerator, chiplet, and data center environments.

Base salary range is $140,000 - $230,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

• Purpose: We invest in what matters. From meaningful-future shaping projects to competitive compensation, we empower you to grow your career while making a lasting impact.
• People: Connection starts within. We collaborate, celebrate wins, and create an environment where everyone can do their best work.
• Possibilities: Our belief shapes what's next. Our technology powers the most reliable and energy-efficient connections around the world – and our team powers new products and markets that come next.

Lead technical evaluations of RFQs and provide guidance on functionality, power, performance, and area tradeoffs.

Partner with product marketing and key customers to define best-in-class technical solutions across product generations.

Help define product and technology roadmaps based on customer needs, market direction, and technical trends.

Translate standards, constraints, and ecosystem trends into architecture goals, requirements, and engineering priorities.

Own the scoping, planning, and execution tracking of design activities and product releases.

Guide architectural decisions with a focus on outcomes, scalability, product impact, and efficient implementation.

Create clear documentation including functional specifications, architecture, microarchitecture, and product requirements.

Develop, debug, and enhance RTL; run lint checks and perform simulation.

Partner with verification to shape test plans, review results, and drive root-cause analysis and resolution of failures.

Lead and contribute to design reviews to ensure technical rigor and design quality.

Perform synthesis tasks including writing timing constraints, running logic synthesis, analyzing reports, achieving timing closure, and implementing ECOs.

Identify risks, dependencies, and roadmap gaps early, and drive cross-team mitigation.

Align engineering, product, and business teams on customer needs, differentiation, and execution.

Communicate technical strategy, priorities, and rationale to internal and external stakeholders.

• 10-12 + years of experience and a strong track record in the following areas:
• Bachelor's or master's degree in electrical engineering, computer engineering, or related field.
• Technical leadership with the ability to plan, manage, and influence engineering, product, and business stakeholders.
• Digital design including state machines, data paths, FIFOs, asynchronous crossings, clock and reset concepts, and high-speed, low-power design.
• Verilog/System Verilog and synthesizable design concepts targeting deep sub-micron technology nodes.
• Systems thinking to evaluate technical tradeoffs and translate them into product direction and prioritized requirements.
• Deep knowledge of networking protocols including 802.3 (Ethernet), PCIe, CXL, UCIe, UALink, and related standards.
• Experience with inter- and intra-chip buses and fabrics, including NoC, coherent/non-coherent fabrics, arbitration, flow control, and latency/bandwidth optimization.
• Comprehensive understanding of architectural impact on logic synthesis,…