RTL Design Engineer

Position: RTL Design Engineer (ASIC/FPGA – Verilog/System Verilog)

Location:

Portland, Oregon (Remote)

Experience:

3 years preferred

We are a leading provider of Display Port and Automotive Ser Des IP cores used in Tier-1 automotive, ADAS, and high-performance SoC designs worldwide. Our IP is integrated into major OEM vehicles and advanced video systems.

• RTL design in Verilog/System Verilog and verification
• Integration of subsystem IP into So Cs
• Developing datapath and control logic
• Working closely with PHY, controller, and interface IP
• Debug and bring-up support with customer teams
• Mixed automotive/video/communication workloads

• High-speed interfaces (DP, MIPI, CSI, HDMI, PCIe, Ser Des)
• Timing closure and synthesis familiarity
• Safety-aware design (ISO
  26262 experience is a bonus)

• Verilog or System Verilog RTL design experience
• Real contribution to an ASIC or FPGA design (not just verification)
• Comfortable looking at waveforms, signals, and bus interfaces
• Experience with design simulation (Questa/VCS) and lint tools

• You want responsibility and technical ownership
• You like small teams where your work matters
• You prefer “engineering reality” over corporate bureaucracy
• You communicate clearly and enjoy solving problems

• You will work directly with experts and learn fast
• You will design real IP used by top-tier customers
• You get ownership, not pigeon-holed tasks
• We are the leaders in Display Port IP, and you will build the next generation

• Linked In profile or resume
• Short summary of your hands-on RTL experience