Senior System Architect

We are seeking an experienced Senior System Architect to define and drive the architecture of advanced silicon systems. This role focuses on system-level design, IP integration, and architectural specifications, enabling next-generation heterogeneous computing solutions on advanced process technologies.

This is a senior technical leadership role with the opportunity to collaborate across hardware, firmware, and software teams while engaging with foundry and design partners.

• Define and document system-level architecture, data flows, memory maps, and transaction models for high-performance computing systems. Define system-level requirements including NOC topology, power domains, clock domains, and interface specifications.
• Coordinate delivery and integration of internal and external IP, including interconnects (e.g. PCIe, DDR, HBM, AMBA CHI NOC), ensuring requirements are met.
• Work with foundry and design service partners to define Statements of Work (SOWs) and manage technical deliverables.
• Define and drive Power, Performance, Area (PPA) targets at the chip, subsystem, and IP levels.
• Collaborate with firmware, software, and verification teams to ensure end-to-end functional and PPA requirements are met.
• Represent architecture decisions across teams and mentor junior engineers.

• Minimum Qualifications
  • MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field
  • 8+ years of relevant industry experience in SoC/ASIC architecture, design, or integration
  • Expert knowledge of system-on-chip (SoC) architecture and design principles
  • Extensive experience defining and documenting system-level architecture requirements and specifications
  • Extensive experience with on-chip interconnect protocols and architectures
  • Excellent written and verbal communication skills and ability to lead technical discussions with vendors and partners
• Preferred Qualifications
  • Extensive experience with RISC-V or Arm CPU architecture, including cache and memory hierarchy design
  • Working knowledge of AMBA Coherent Hub Interface (CHI) network-on-chip IP, with understanding of coherent interconnect architectures for multi-core and heterogeneous systems
  • Working knowledge of advanced packaging 2.5D/3D integration technologies, chiplet architectures, and die-to-die interfaces (UCIe, BoW, CoWoS)
  • Basic familiarity with foundry ecosystems and design service providers
  • Working knowledge of PCIe, UCIe, DDR/LPDDR, HBM, or other industry-standard interfaces Extensive proficiency in Python or similar scripting languages for design automation and analysis

• Lead impactful architecture decisions shaping next-generation heterogeneous computing
• Competitive compensation & benefits package
• Collaboration with talented engineers passionate about cutting-edge CPU technologies.
• Opportunities for professional growth in an innovative, fast-paced environment
• A flexible and inclusive work culture based in Portland, OR

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