Senior CPU RTL Engineer, Silicon

By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA;
Austin, TX, USA;
Portland, OR, USA;
Poughkeepsie, NY, USA
.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or System Verilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power including low‑power design techniques.

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

The US base salary range for this full‑time position is $156,000–$229,000 plus bonus, equity, and benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

• Contribute to CPU frontend designs, emphasizing microarchitecture and Register‑Transfer Level (RTL) design for the next generation CPU.
• Propose performance‑enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade‑off studies. Communicate pros and cons of microarchitecture enhancements and facilitate final decision making.
• Deliver designs meeting Power, performance and area (PPA) goals with production quality.
• Become familiar with state‑of‑the‑art techniques for any one processor functional block. Interpret the techniques into design constructs and languages to provide guidance to and participate in the performance modeling effort.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See Google’s EEO Policy and EEO is the Law.

If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.