ASIC​/FPGA Verification Engineer III

Overview

Job Description Join Our Team as a ASIC/FPGA Verification Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment.

Location:

this position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in the following locations:
Denver CO or Highlands Ranch CO;
Sunnyvale CA. You will work a flexible 9x80 schedule in the office full-time.

Space is a critical domain, connecting our technologies, our security, and our humanity. We’re creating future-ready solutions, focusing on resiliency and urgency through our 21st Century Security vision. We’re advancing spacecraft and the workforce to fuel the next generation. Join us in shaping a new era in space and find a career that’s built for you.

• Support other aspects of ASIC and FPGA development such as architecture, design, analysis, and test.
• Support technical reviews and be able to present to internal and external customers.
• Devise a unique verification plan for a given design.
• Use System Verilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
• Document verification plan and results.
• Work with an independent verification team to resolve bugs found in the design.

• ASIC/FPGA verification experience with modern verification methodologies such as UVM, OVM or VMM.
• 3+ years professional experience.
• While no clearance is needed to start in this position, you will need to obtain and maintain a DoD Secret clearance
  , thus ship is required.
• Experience in the verification of FPGA and/or ASIC devices.
• HDL programming experience with VHDL, Verilog, and/or System Verilog.

• Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
• Knowledge of space-grade/qualified FPGAs and ASICs and toolsets including AMD/Xilinx Vivado or Microchip Libero.
• Knowledge of digital design, development, and simulation.
• FPGA engineering process improvement activities.
• Metrics collection, analysis, and reporting to senior leadership.

EEO Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics.

The application window will close in 90 days; applicants are encouraged to apply within 5 - 30 days of the requisition posting date in order to receive optimal consideration. At Lockheed Martin, we use our passion for purposeful innovation to help keep people safe and solve the world’s most complex challenges.

Other important information and work schedule options are provided below.

• Work Schedule Information
  :
  Lockheed Martin supports a variety of alternate work schedules that provide additional flexibility to our employees. Schedules range from standard 40 hours over a five day work week while others may be condensed. These condensed schedules provide employees with additional time away from the office and are in addition to our Paid Time off benefits.
• National Pay Statement
  :
  Pay rate ranges are provided by location and reflect the final work location; salary information is a general guideline.
• Premium Pay Statement
  :
  Pay rate ranges are provided by location and reflect the final work location; salary information is a general guideline.

This position is incentive plan eligible. By applying to this job, you are expressing interest in this position and could be considered for other career opportunities where similar skills and requirements have been identified as a match.