Junior Engineer, FPGA

Responsibilities

• This role requires experience with FPGA design using hardware description languages (Verilog/VHDL) and/or high-level synthesis (HLS) techniques
• The role involves the development of accelerated logic targeting FPGAs
• The applicant must have the ability to parse through FPGA design files and be able to integrate proprietary IP designs
• With the current pace of hardware evolution there is a constant update in the availability of optimized front ends and peripherals that the candidate would have to read into and help integrate
• The role would also need the applicant to be comfortable making IP datasheets and documentation

• Experience in Testbench development:
  Develop and maintain test-benches for new or current IPs
• Experience in targeting/retargeting designs to FPGA boards
• Experience coding and ability to understand Verilog, VHDL, System Verilog and C
• Experience in building and troubleshooting designs to create timing clean images
• Experience in building multi-clock domain, synchronize and a-synchronize logic designs
• Experience in evaluating and creating design documentation/data sheets
• Experience developing and deploying designs on Xilinx boards.

• FPGA design
• Verilog
• VHDL
• high-level synthesis
• Testbench development
• System Verilog
• C programming
• timing analysis
• multi-clock domain design
• Xilinx boards

• documentation
• integration
• troubleshooting
• communication