Staff Layout Design Engineer

Staff Layout Design Engineer

Experience Level: Professional Job Type: Regular

Location:

Raleigh, NC, US, 27560 Sacramento, CA, US, 94204 Tallahassee, FL, US, 32302 Sacramento, CA, US, 94204 Denver, CO, US, 80014 Austin, TX, US, 73344

Qorvo supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. In this position, you will work closely with design engineering groups to complete the layout and verification of high-performance Switches, Power Management Devices, and Integrated Products using Cadence Virtuoso XL and Mentor's Calibre tools.

Responsibilities:

• Work closely with design engineers to ensure proper circuit performance
• Design analog and RF layout
• Understand device matching techniques
• Excellent teamwork skills, including written and verbal communications, with both local and remote design teams
• Exceptional layout planning and integration skills from small block to full chip

Skills and

Qualifications:

• Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience
• Ability to layout analog circuitry in a size/time constrained environment
• Understand layout techniques such as common centroid, matching, isolation, and the use of dummy devices
• Ability to solve design problems using technical skills, intuition, and creativity
• Proficiency in floor planning and assembly from block to full chip level
• Working knowledge of Cadence and Mentor Verification tools
• Strong LVS troubleshooting and debug skills
• Demonstrated ability to work individually and in a team-orientated environment

Preferred Skills and

Qualifications:

• BSEE/BS Engineering Technology or related program
• Comfortable with CMOS and SOI technologies across multiple foundry PDKs
• Demonstrated ability to contribute ideas for improved schematic and layout interaction
• Schematic entry for dummy devices, resizing devices, and debugging LVS issues

This position is not eligible for visa sponsorship by the Company. Competitive base salary commensurate with experience: $144,300 - $187,600, relevant for the California Bay Area (subject to change dependent on physical location). Posted salary ranges are made in good faith. Qorvo reserves the right to adjust ranges depending on the experience/qualification of the selected candidate as well as external competitiveness and internal comparability.

Base compensation is one element of Total Rewards offered e information on the Total Rewards package can be shared upon request.

Qorvo is an Equal Employment Opportunity (EEO) employer and welcomes all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.