DRAM Firmware​/Integration Engineer

The DRAM Firmware/Integration Engineer is responsible for developing, validating, and integrating DRAM drivers for SSD firmware platforms. This role requires expertise in DRAM IP, PHY IP, ECC, and DDR4/DDR5 protocols. The engineer will configure and validate DRAM operations, develop test procedures, and guide debugging efforts to resolve issues. Collaboration with cross-functional teams and strong technical leadership are essential to ensure successful product outcomes.

• Develop and integrate DRAM drivers for SSD firmware platforms
• Understand and validate DRAM IP on the controller side, including read/write, gate training, and write leveling
• Configure DRAM PHY IP and develop expertise in DRAM ECC
• Work with DDR4/DDR5 protocols including mode register configuration, initialization, power states, and refresh policies
• Develop test procedures and tools for DRAM validation and debugging
• Guide debug efforts to resolve DRAM issues efficiently
• Collaborate with cross-functional teams and provide technical expertise to internal and external partners
• Document requirements and track schedules related to product development
• Build strong relationships across teams to support collaboration and knowledge sharing

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related discipline
• Minimum of 3 years of experience in DRAM architecture, operation, and integration
• Proficiency with memory testing tools and software
• Knowledge of signal integrity, high-speed signal fundamentals, and simulation techniques
• Hands‑on experience with lab tools such as oscilloscopes, power supplies, and soldering equipment
• Strong analytical skills with the ability to communicate complex concepts
• Strong planning, documentation, and organizational skills
• Excellent communication, interpersonal, and problem‑solving abilities
• HW or FW project management and leadership skills
• Ability to work independently and in team environments

• Expertise in DDR4/DDR5 protocols and advanced DRAM ECC
• Experience in debugging DRAM issues with structured methodologies
• Familiarity with cross‑functional collaboration in large engineering teams