Senior Firmware Engineer; FTL

Design and Maintain FTL Architecture

• Develop and maintain the Flash Translation Layer (FTL) including I/O flow, Garbage Collection, and Wear Leveling algorithms to ensure data integrity and maximize NAND endurance.

• Implement bad block detection, isolation, and data migration mechanisms to manage block lifecycle.
• Design robust metadata structures to support fast mapping table reconstruction and system boot.

• Prevent and mitigate NAND‑related issues such as read disturb, program/erase failures, and retention loss.
• Implement RAID encode/decode flows to guarantee data reliability.

• Design and implement power‑loss protection algorithms to maintain data consistency and metadata integrity during unexpected shutdowns.
• Verify and optimize power‑loss recovery flow to ensure fast and reliable system startup.

• Optimize channel/die/plane access scheduling and parallelism to improve throughput and reduce latency.
• Enhance DRAM/SRAM usage efficiency and reduce write amplification for better endurance and performance.

• Develop and analyze FTL traces and logs for performance profiling and issue root‑cause analysis.
• Conduct stress testing, mixed workload testing, power‑fail tests, and corner‑case verification to ensure firmware stability and reliability.
• Collaborate with Validation, Hardware, and ASIC teams to resolve cross‑functional issues and ensure system robustness.

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• At least 3 years’ work experience in each of the following areas:
  • Software/firmware application engineering
  • SSD controller/firmware architecture
  • Strong experience in C/C++ programming and data structures
  • Hands‑on experience with JTAG/ICE debuggers
  • Experience with version control software like Git
  • Competent to work independently as well as in a small team collaboration environment
  • Willingness to learn fast and execute as a team player
  • Good oral, written, and presentation skills for communication and documentation
  • Ability to work independently with a minimum of day‑to‑day supervision

• Ability to operate logic analyzer, oscilloscope, and bus protocol analyzer
• Familiarity with SATA/PCIe (NVMe) protocols
• Familiarity with NAND flash protocols
• Linux system debug experience
• Fluent in reading and writing Mandarin (preferred)

Work Location:

Rancho Cordova, CA

Estimated Base Pay Range (USD) for this full‑time position: $150,000 - $210,000 per annum. The exact starting base pay will be determined based on job‑related skills, experience, qualifications, work location and market conditions.

• Highly competitive salaries differentiated by performance.
• Annual merit increases.
• Year‑end bonus.
• RSU for eligible employees.
• Invention and Patent Awards.
• 401(k) employer matching.
• Length of service awards.
• Comprehensive health insurance plans for eligible employees and dependents.

For applying or for more information about the recruitment, please contact: