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RTL Design Engineer - Next-Gen Mixed-Signal ASICs

Job in Reading, Middlesex County, Massachusetts, 01814, USA
Listing for: Teradyne
Full Time position
Listed on 2026-08-22
Job specializations:
  • Engineering
    Hardware Engineer, Electronics Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 123000 - 197000 USD Yearly USD 123000.00 197000.00 YEAR
Job Description & How to Apply Below

Teradyne in North Reading, MA, seeks an experienced RTL Designer to join the Silicon Technology Engineering group. You will contribute to advanced node ASIC development, collaborating with Analog and architecture teams across specification, design, verification, physical design, and silicon bring-up.

The role emphasizes high-speed memory, timing closure, and automation via scripting. Minimum 5+ years in EE with Verilog RTL, CDC/STA, and memory/serial interfaces; strong collaboration with

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