ASIC and Logic Design Engineering Manager; Compute Test, North Reading

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Date: Aug 28, 2026

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results.

The Logic Design  Managerisresponsible for leading a team of developersindesigning and verifyingFPGA’sfor Teradyne Compute Test  Division’s  this role you willlead a team of~4-6engineers in a fast-paced environmenttohelp the organization meet key business needs.

Requires closecollaborationwiththeotherFPGA design and verification managers and with otherengineeringdisciplinesincludingmixed signalASIC design,circuit board design,software and systemsengineeringtospecify andimplementnew products.

You should have hands-on experience with complexFPGA(and preferably digitalASIC)
SOC designs for real-world products. Youalso should have a proven track recordof managing engineering teams towardtimelydeliverables and successful project completion.

Lead multiple simultaneous(typically 2-3) FPGA or digital IP development projects.

Typically includes oversight of some remote resources.

Planning and trackingofproject scheduleandbudget.

Manage project staffing levels including bothfull time and contract resources.

Represent theFPGAteam on project core teamsand atprogram reviews.

Contribute to FPGA implementation (i.e.code RTL blocks) as needed.

Provide technical support for HWsustainingissues.

Set goals, provide coaching and manage compensationofa4-6personteam.

Contribute toFPGAteam process improvement initiatives.

Collaborate withother engineering and business disciplines to ensure thatFPGA and IPdeliverablessatisfy all product requirements.

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

• BSEEorMSEEand
  12+ years of relevant experience in DigitalFPGAdesign and integration(DigitalASICexperience is a plus).
• Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects from concept, architecture exploration, design implementation and lab validation to production release.
• Extensive experience coding RTL(verilogpreferred).
• Extensive experienceusingdigital simulation tools (Cadence preferred).
• Extensive experienceusingstatic timing analysis tools.
• Experience designing with the following: PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES
• Experience with eitherAMDorAlteraFPGAs and development tools(Vivado/Quartus), preferably both.
• Experienceusingdigital design qualitytoolse.g.LINT, CDC.
• Experience with bug tracking tools (Jiraetc.)
• Experience with source control systems (Clearcase, Git, CVS) and continuous integration.
• Familiarity with digital verification tools and methodologies (preferably UVM).
• Experience with projectschedulingtools (e.g.Microsoft project)
• Experience with embedded processors and digital signal…