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FPGA & ASIC Compute Test Design Manager

Job in Reading, Middlesex County, Massachusetts, 01814, USA
Listing for: Teradyne
Full Time position
Listed on 2026-08-31
Job specializations:
  • Engineering
Salary/Wage Range or Industry Benchmark: 156000 - 249000 USD Yearly USD 156000.00 249000.00 YEAR
Job Description & How to Apply Below

Teradyne North Reading is seeking an ASIC and Logic Design Engineering Manager to lead a 4–6 person FPGA/digital IP team. You will design and verify FPGA/ASIC components, collaborate with multiple engineering disciplines, and drive timely, high-quality deliverables for next-generation Compute Test products.

You will oversee staffing, planning, and budget, contribute to RTL code, and mentor engineers while coordinating with cross-functional teams to meet product requirements.

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