FPGA Verification Engineer

Role:
Design Verification Lead – System Verilog / UVM

Location: Redmond, WA (Fully Onsite)

Type: Long-Term-Contract or Full-Time

Job Description:

Seeking a highly experienced Design Verification Lead with strong hands‑on expertise in System Verilog and UVM methodology for IP/Module-level verification. The ideal candidate will have a proven background in building UVM environments from scratch, leading verification teams, and deep knowledge of AMBA protocols. This role requires both technical leadership and hands‑on verification expertise in a fast‑paced, silicon development environment.

• Lead and execute IP/Module-level Design Verification using System Verilog and UVM
• Architect, develop, and maintain UVM test benches from scratch (not in‑house POCs or training projects)
• Define and own verification strategies, including test plans, coverage models, and verification closure
• Integrate and bring up Verification IPs (VIPs) within UVM‑based environments
• Perform functional, protocol, and corner‑case verification for complex designs
• Debug complex design and testbench issues across RTL, UVM components, and VIPs
• Lead and mentor a Design Verification team of 5+ engineers
• Conduct code reviews, verification reviews, and sign‑off activities
• Collaborate closely with design, architecture, and validation teams
• Drive verification best practices and continuous improvements

• 8+ years of hands‑on Design Verification experience
• Strong expertise in System Verilog and UVM
• Proven experience in developing UVM test benches from scratch for IP verification
• Deep working knowledge of AMBA protocols (AXI / AHB / APB)
• Experience in VIP integration and bring‑up
• Strong background in test planning, functional & code coverage, and debugging
• Experience in porting legacy Verilog/VHDL verification environments to UVM
• Demonstrated experience leading Design Verification teams (minimum 5 members)
• Ability to work onsite and collaborate with cross‑functional teams

• Experience working on large‑scale SoC or complex IP designs
• Exposure to low‑power verification and performance verification
• Prior experience working with Tier‑1 semiconductor or FAANG clients
• UVM‑from‑scratch experience is mandatory
• Leadership experience is required (hands‑on leads are acceptable)
• Candidates without real‑world IP verification experience using UVM will not be considered
• VIP integration experience is preferred; leadership experience is non‑negotiable

Seniority level: Mid‑Senior level

Employment type: Contract

Job function: Quality Assurance

Industries: IT Services and IT Consulting

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