Hardware Design Engineer

Overview

Purpose of the Team:
The purpose of this team is working on analog mixed signal IPs for in-house SoC designs, specifically for data center processors, focusing on advanced CMOS technology such as FinFET and gate-all-around.

Key projects:
This role will contribute to designing and creating layouts for analog mixed signal circuits in advanced CMOS nodes (2-3nm), supporting data center processor development.

Typical task breakdown and operating rhythm:
The role will consist of 80% of the role as heads-down design/layout work, with 20% spent in meetings. The focus is on analog layout rather than custom digital.

What makes this role interesting?:
The role offers the opportunity to work on cutting-edge analog layout in the most advanced CMOS technologies (FinFET and gate-all-around, 2-3nm), which is rare and highly valued in the industry.

• Years of Experience
  
  Required:
  
  5+ overall years of experience in the field.
• Degrees or certifications required: no degree is required to be eligible for this role.
• Best vs. Average:
  The ideal resume would contain recent experience on CMOS layout and verification on advanced FINFET and GAA. Recent experience with advance PSMC notes is a big plus.
• Performance Indicators:
  Performance will be assessed based on layout productivity

• Analog circuit layout in advanced CMOS (FinFET/gate-all-around, 2-3nm) – Minimum 4 years.
• Proficiency with layout tools (Cadence Virtuoso, Calibre) – Minimum 4 years.
• Understanding of analog layout techniques (matching, shielding, reliability, parasitic optimization) – Minimum 4 years.

• Execute full-custom layout for analog and mixed-signal blocks including ADCs, DACs, PLLs, LDOs, comparators, and temperature sensors.
• Collaborate with circuit designers to optimize layout for performance, area, and power.
• Perform floor planning, block-level routing, and macro-level assembly.
• Conduct physical verification using tools like Cadence Virtuoso, Synopsys Custom Compiler, and Calibre.
• Address DRC/LVS, EMIR, and DFM issues and ensure layout meets manufacturing and reliability standards.
• Support tape-out activities and post-layout simulation reviews.
• Document layout strategies and contribute to design reviews.