PIC Characterization & Design Engineer

Job Description

We are seeking a passionate Optical Engineer to join our research and development team. This role focuses on delivering state‑of‑the‑art near‑to‑eye display system technologies. The ideal candidate will have expertise in novel integrated photonics device design and metrology, gained through a Ph.D. or industry experience.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances.

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Design and develop complete Photonic Integrated Circuits (PICs), from fundamental component blocks to full‑circuit implementations, with a strong emphasis on active device integration.

Generate, verify, and prepare fabrication‑ready layout files, ensuring compliance with foundry Process Design Kits (PDKs) for external fabrication.

Conduct systematic design analysis, including optimization and parametric studies, to guide design decisions.

Support the entire design‑to‑fabrication pipeline, from initial concept through tapeout, coordinating closely with cross‑functional teams and external partners.

Collaborate with program leadership, Technical Program Managers (TPMs), and researchers on PIC designs that align with overall program objectives.

MS or Ph.D. degree in Electrical Engineering, Optical Sciences, Physics, or a closely related field.

3+ years of hands‑on experience in the design, simulation, and layout of PICs for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.

3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both component and circuit‑level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).

2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.

2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.

1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non‑idealities). 3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.

3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.

3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).

2+ years of experience utilizing photonic circuit‑level simulation tools (e.g., Lumerical Interconnect, Synopsys Opt Sim, or VPIphotonics) for system‑level performance evaluation.

2+ years of experience in photonic device characterization and test, including both optical and electro‑optic measurements.

1+ years experience with fiber optics, free‑space optics, PIC packaging, and comprehensive device characterization.

1+ years experience with semiconductor fabrication processes and a deep understanding of process‑induced performance limitations, such as optical losses, sidewall roughness, and process variability.

Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementing effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).