Technical Program Manager

Technical Program Manager I - Display Silicon & uLED Programs

Location: Onsite at Redmond, WA or Sunnyvale, CA

Competitive Compensation: $65/hr (W2)

We are seeking a highly organized and execution-focused Technical Program Manager (TPM) to lead complex display silicon and uLED backplane development programs from early concept through high-volume manufacturing. This role sits at the intersection of engineering, operations, sourcing, and external vendor management, ensuring seamless execution across multiple internal and external stakeholders. As a TPM supporting Display Silicon programs, you will serve as the central coordination point between display silicon engineering teams, cross‑functional partners, and external foundry and silicon vendors.

You will drive program schedules, manage dependencies, mitigate risks, facilitate communication, and ensure critical decisions are effectively communicated across all impacted teams. This is an exciting opportunity to work alongside world‑class silicon, packaging, test, sourcing, and product engineering teams developing the technologies that power next‑generation AR and smart glasses products.

• Internal Cross‑Functional Coordination:
  Run recurring meetings and program reviews that bring uLED, test, packaging, and sourcing teams into alignment. Track decisions, surface dependencies and risks, and resolve gaps before they require escalation.
• External Vendor Interface Management:
  Run recurring meetings and program reviews with external foundry and silicon vendor partners, including joint working sessions, milestone reviews, and face‑to‑face meetings. Drive vendors to execute against specified requirements, maintain integrated program schedules that bridge milestones with vendor‑committed dates, and surface misalignment early.
• Program Tracking and Reporting:
  Maintain authoritative trackers for program status across internal and external work streams. Produce milestone readouts and decision items for silicon leadership and cross‑functional stakeholders.
• Risk Management:
  
  Maintain a living risk register covering technical execution, vendor delivery risk, IP and confidentiality concerns, and schedule risk. Drive mitigation plans with named owners and resolution dates. Produce risk summaries for leadership readouts.

• 1–3 years of experience as a technical program manager, or equivalent project management experience in a hardware or silicon development environment.
• B.S. in Electrical Engineering, Computer Engineering, Physics, Materials Science, or a related engineering discipline, or equivalent experience.
• Demonstrated ability to coordinate execution across multiple engineering teams (e.g., silicon, hardware, test, packaging) and translate high‑level commitments into actionable schedules with owners and dates.
• Experience working with external vendors, contract manufacturers, or foundries.
• Exposure to hardware development phases (e.g., prototype, qualification, mass production).
• Strong written and verbal communication skills, with experience presenting program status and risk to engineering and cross‑functional stakeholders.
• Analytical and problem‑solving skills, with the discipline to drive decisions from incomplete information and follow through on action items across many stakeholders.
• Comfort operating in ambiguous, fast‑paced environments with shifting requirements and tight launch timelines.

• Experience supporting semiconductor programs across foundry, OSAT, or silicon vendor interfaces.
• Familiarity with display silicon, uLED, or related electro‑optical technologies.
• Experience managing programs with multiple external vendors.
• Experience working across timezones with international foundry, OSAT, or vendor partners.
• Working knowledge of program tracking and milestone reporting tools (e.g., Smartsheet, Jira) for cross‑functional hardware programs.
• Experience translating engineering status and risk into briefings for sourcing and engineering leadership.
• Experience supporting consumer device programs from prototype validation through mass production.

Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position.

These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.