Electrical Engineer

Job Title

You will be responsible for static timing and some physical design tasks at block, sub-chip and/or full chip level. This will include ownership and responsibility for activities including: synthesis, SDC constraints generation, and timing closure through manual and automated ECOs. You will be involved in STA flow and automation development as well as tapeout reviews. You are expected to take ownership and responsibility for your assignments, be able to work with limited direction, have attention to detail and be able to provide crisp status of progress, issues, and risks on the program to the management team.

• Bachelor's or Masters in Electrical or Computer Engineering or related field with 7+ years of experience
• Experience in tape-outs of complex ASICs in leading-edge technology.
• Deep expertise in Prime Time usage, timing closure and constraints
• Experience in setup and integration of test-mode timing constraints and debug, particularly Tessent-based.

• Experience with high frequency and low power implementation methodology.