Quantum Systems Digital Design Engineer II

** Overview*
* Microsoft is the world's center of expertise on topological quantum computing.  We are building a scaled, fault‑tolerant quantum computer grounded in topological qubits and integrated end‑to‑end with the Azure Quantum software stack.

As a 
** Quantum Systems Digital Design Engineer II** , you'll collaborate closely with quantum physicists, systems software, RF/EE, and manufacturing/production to define, design, and deliver FPGA‑based, ultra‑low‑latency digital subsystems that sit at the heart of our topological quantum engine-spanning readout classification, error‑decoder acceleration, room‑temperature front‑ends for cryogenic control, high‑speed interconnects, and precision clocking networks. Your work will directly impact logical‑qubit stability, throughput, and system scale.

At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence, and quantum information technology. Microsoft Quantum will change the world of computing and help solve some of humankind's currently unsolvable problems. For more information about our team, visit   .

** Responsibilities*
* + Design & implement RTL for streaming, low‑latency pipelines (e.g., readout classifiers, syndrome aggregation, and QEC decoder kernels) in Verilog/System Verilog, including resource/performance trade‑offs and power/thermal considerations.

+ Design and implement high‑speed interconnects between subsystems (AXI4/AXI‑Stream, JESD
204(B/C), Aurora, Ethernet/UDP, PCIe), including SERDES configuration, link bring‑up, and throughput/latency tuning.

+ Design robust clocking & CDC strategies (MMCM/PLL trees, jitter budgets, multi‑domain timing closure, async FIFOs, metastability analysis) for deterministic performance.

+ Co‑design hardware/firmware/software boundaries (register maps, DMA, interrupt models, driver interfaces) with control/readout software and instrument teams; contribute to system‑level design reviews.

+ Verification and validation: develop simulation and constrained‑random tests (SV/UVM or equivalent), build on‑board diagnostics (ILA/Chip Scope), and execute lab bring‑up with scopes, VNAs, LA/SC, and RF instruments.

+ Tool flow & CI: own synthesis/implementation (Vivado/Vitis or Quartus/Prime), timing sign‑off, and reproducible, scripted builds (Tcl/Python) integrated with Git/Azure Dev Ops CI/CD.

+ Quality & documentation: produce clear design docs, interface specs, and bring‑up guides; participate in rigorous code/design reviews and post‑silicon/post‑fabrication retros.

+ Embody our Culture  () and Values ()

** Qualifications*
* ** Required*
* + Master's Degree in Physics, Electrical/Computer Engineering, or related field AND 1+ years experience in industry or in a research and development environment

+ OR Bachelor's Degree in Physics, Electrical/Computer Engineering, or related field AND 2+ years experience in industry or in a research and development environment

+ OR equivalent experience.

+ This position requires verification of citizenship or other protected status to meet legal requirements of the role. If the role requires US citizenship, as indicated in the job description, a valid US passport must be provided to verify your citizenship. If the role requires US Person status, as indicated in the job description, US citizens must provide a valid US passport for verification while lawful permanent residents, refugees, and asylees may complete this verification using green cards or other status documents, as applicable.

** Additional or

Preferred Qualifications *
* + 3+ years building production FPGA designs in Verilog/System Verilog (or VHDL), including synthesis, P&R, and static timing analysis on Xilinx/AMD (Ultra Scale+/Versal/RFSoC) and/or Intel platforms.

+ Proven delivery of low‑latency, streaming datapaths (DSP, filtering, classification, or decoder‑like pipelines) with tight timing closure at high clocks.

+ Hands‑on with high‑speed I/O and protocols: AXI4/AXIS, JESD
204(B/C), Aurora, multi‑gig SERDES; competent in link bring‑up, eye margins, and error budget…