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SOC Architect, Reality Labs Silicon

Job in Redmond, King County, Washington, 98052, USA
Listing for: Meta
Full Time position
Listed on 2026-09-07
Job specializations:
  • Engineering
    Hardware Engineer, Systems Engineer, AI Engineer (Applied/Software), Electronics Engineer
Salary/Wage Range or Industry Benchmark: 220000 - 300000 USD Yearly USD 220000.00 300000.00 YEAR
Job Description & How to Apply Below

Reality Labs focuses on delivering Meta's vision through creating advanced AR/AI enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual worlds will mix and match throughout the day.

We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

As an SoC Architect, you will play a key role in driving top-level chip architecture that meets the power and size constraints of wearable devices. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience8+ years of experience in SoC architecture, microarchitecture definition, or system-level hardware design for consumer electronics or mobile/wearable platforms

Experience architecting heterogeneous SoCs, encompassing CPU, GPU, neural processing, and hardware accelerator subsystems

Expertise with high-speed I/O interfaces such as PCIe, USB, and LPDDRExperience with memory subsystem architecture, including cache hierarchy design, DRAM interface optimization, and on-chip interconnect (NoC) design

Experience collaborating across hardware, firmware, and software disciplines to drive hardware-software co-design for real-time or latency-constrained workloads Experience architecting silicon for AR, VR, or wearable devices with stringent power and thermal constraints

Experience with AI/ML accelerator architecture and optimizing memory hierarchy for neural network workloads for on-device inference

Familiarity with advanced process node design considerations (e.g., 5nm and below) and their implications for SoC architecture decisions

Experience with system MMUs and hardware security

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