Principal ASIC Design Engineer

About Us

At Cognichip, we are building the next-generation AI-enabled solutions to empower semiconductor design engineers with a 10x productivity boost through specialized generative models, agentic workflows and seamless integration with high-performance EDA engines.

Principal ASIC Design Engineer

We are seeking a Principal ASIC Design Engineer at the intersection of silicon design and artificial intelligence. This senior IC role focuses on re-imagining chip design flows with an AI-first mindset, and charting the path to incorporate enterprise and know-how into intelligent systems for AI-native production-quality chip design and verification. The ideal candidate combines deep silicon expertise, microarchitecture, RTL, DV, and EDA workflows, into structured AI-driven and tool-aware processes.

• Translate chip-design expertise (RTL/DV best practices, micro-architectural patterns, failure modes) into reusable, AI-consumable knowledge bases and agent playbooks.
• Identify bottlenecks in advanced chip design process and devise novel models, tools, and to rethink workflows to drastically change the outcome.
• Define EDA tool usage strategies and wrappers for AI-native workflows.
• Define evaluation strategies suitable for AI systems to enhance performance and grounding.

• 15+ years of hands‑on experience in Chip Design and Physical Design.
• Proven expertise in Digital IC, ASIC, or SoC design; strong proficiency in System Verilog RTL and STA.
• Solid understanding of microarchitecture concepts: pipelines, FIFOs, DMA engines, caches, and on‑chip interconnects.
• Deep familiarity with the full design cycle: lint, CDC/RDC, functional simulation, and STA.
• Ability to articulate design tradeoffs and debug complex RTL issues.
• Proficiency in Python; experience integrating tools into automated workflows.

• Demonstrated experience with AI/ML systems (of any kind), prompt and context engineering.
• Ability to translate complex silicon design problems into structured, executable and verifiable components in agent workflows.
• Experience with AI‑assisted EDA tools or ML/chip design research.
• Contributions to open‑source chip design, EDA tooling, or AI/ML infrastructure.

• A foundational role in how AI transforms chip design.
• A collaborative environment where deep silicon expertise meets cutting‑edge AI research.
• Competitive compensation, equity, and benefits.
• Flexible work with access to world‑class compute and EDA infrastructure.

We are an equal opportunity employer committed to building a diverse and inclusive team.